1. Technical Field
The present invention relates to semiconductor design technology, and more particularly, to a pin removal mode signal generation circuit and a semiconductor apparatus including the same.
2. Related Art
In order to test a packaged semiconductor apparatus, a test board and I/O pins are utilized. For memory chips, a plurality of memory chips are connected to a test board to perform tests concurrently, during which addresses and commands are inputted to the respective memory chips. Output signals of the memory chips are then measured to determine whether the corresponding memory chips failed or passed.
FIG. 1 is an address input waveform diagram of a conventional semiconductor apparatus during a test mode.
A packaged semiconductor memory apparatus has a plurality of pins defined in the specification. Referring to FIG. 1, the semiconductor memory apparatus receives addresses address0 to address14 corresponding to a plurality of address input pins A0 to A14 during the test mode. The semiconductor memory apparatus latches the addresses address0 to address14 in synchronization with a rising edge of a clock signal received through a clock input pin CLK.
FIG. 2 is a timing diagram when the conventional semiconductor memory apparatus enters the test mode.
With the diversification of functions, semiconductor memory apparatuses are designed to implement various operation modes. In particular, a semiconductor memory apparatus such as synchronous DRAM includes a mode register set circuit to set various operation modes. FIG. 2 illustrates an example of a method for activating a test mode signal TSET such that the mode register set circuit provided in the semiconductor memory apparatus enters the test mode.
A plurality of test set commands TMRS0 to TMRS2 are received through a command input pin CMD in synchronization with a clock signal received through a clock input pin CLK. When preset addresses are received through address input pins A7 to A10 when the plurality of test set commands TMRS0 to TMRS2 are received, an activated test mode signal pulse TSET is generated. Accordingly, the semiconductor memory apparatus enters the test mode.
Various methods for reducing test time required for a semiconductor memory apparatus have been proposed. The methods may include an address pin removal mode in which only a part of a plurality of address pins is used to connect a plurality of semiconductor memory apparatuses to a test board. In the address pin removal mode, only a part of the address pins are connected to the test board, and addresses are sequentially inputted to the connected address pins to perform tests. As a result, since a larger number of semiconductor memory apparatuses may be connected to the test board than during a normal test mode, more tests may be performed at the same time.
The standardization of a method for controlling a semiconductor memory apparatus to enter the address pin removal mode, as well as hardware developments to minimize additional area and to allow the method to occur in a stable manner, is in the process of being developed.